The configuration of gate shown in figure is equivalent to
NAND
XOR
OR
none of these
Y = (A+B).(A.B¯) = A+B.A¯+B¯ A.A¯+A.B¯+B.A¯+B.B¯ = 0+A.B¯ + B.A¯ + 0
⇒ Y = A.B¯ +B.A¯ ⇒ XOR gate